module denqueueUpdateDeMuxer16 (
    input wire clk,
    input wire rst,
    input wire dequeue_head_new_en_in,
    input wire [5:0] dequeue_head_new_port_in,
    input wire [5:0] dequeue_head_new_priority_in,
    input wire [15:0] dequeue_head_new_value_in,
    output reg [15:0] dequeue_head_new_en_out,
    output reg [5:0] dequeue_head_new_priority_out [0:15],
    output reg [15:0] dequeue_head_new_value_out [0:15]
);
    
    integer i;

    //数据分发
    always @(posedge clk) begin
        if (rst) begin
            //复位信号拉高时，将所有的使能信号拉低
            dequeue_head_new_en_out <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                dequeue_head_new_priority_out[i] <= 0;
                dequeue_head_new_value_out[i] <= 0;
            end
        end
        else begin
            //按照target_port将数据转发到对应端口
            if (dequeue_head_new_en_in) begin
                dequeue_head_new_en_out <= (1 << dequeue_head_new_port_in);
                dequeue_head_new_priority_out[dequeue_head_new_port_in] <= dequeue_head_new_priority_in;
                dequeue_head_new_value_out[dequeue_head_new_port_in] <= dequeue_head_new_value_in;
            end
            else begin
                dequeue_head_new_en_out <= 16'h0000;
            end
        end
    end
endmodule